PLDs may be used to implement large systems that include millions of gates and megabits of embedded memory. The complexity of large systems often require the use of EDA tools to manage and optimize their design onto physical target devices. Of the tasks required in managing and optimizing design, satisfying timing and placement constraints of a system is often the most important and the most challenging. In order to satisfy timing and placement constraints, several iterations are often required to determine how components in logic blocks are to be grouped and where these logic blocks are placed on the target device.
Automated placement algorithms in EDA tools perform the time-consuming task of managing and optimizing designs onto physical devices. However, in some occasions, standard automated placement algorithms found in off the shelf EDA tools are incapable of finding solutions that specialized placement algorithms can find. In addition, some designs may require additional placement modifications to be provided. Modifications to placement techniques are often necessary to identify and address fitting issues that automated algorithms are slow to or even sometimes unable to identify. Current EDA tools, however, require that placement modifications be provided after a compilation process by the EDA tools and that the compilation process be run again thereafter. Compilation processes may require hours of time before completion. When multiple iterations are required to find a solution, this translates into several hours of waiting time.
Thus, what is needed is a method and apparatus for extending the capabilities of tools used for designing systems on PLDs. This improved method and apparatus should provide the user with more flexibility in the design process while reducing wait time in the compilation process.